The present invention relates to heterojunction bipolar transistors and fabrication methods thereof.
The bipolar transistors have an excellent feature that their current drive performance is superior to that of the field effect transistors. Because of it, research and development of the bipolar transistors using not only silicon but also compound semiconductors such as gallium arsenide is actively engaged in recent years. In particular, the heterojunction bipolar transistors that use compound semiconductors (referred to as HBTs hereinafter) have such an advantage as enabling to hold the emitter injection efficiency at a high level even when the base is doped to a high concentration by making the gap of the forbidden band of the emitter to the greater than that of the base.
Next, an example of the collector-up type HBT will be described following the steps of its fabrication.
First, an n-Al.sub.0.25 Ga.sub.0.75 As layer (emitter layer), a p-GaAs layer (base layer) and a n-GaAs layer (collector layer) are sequentially formed by a molecular beam epitaxy method- (referred to as MBE method hereinafter) on a semi-insulating substrate consisting of GaAs. Next, after forming a collector electrode of a predetermined pattern having a silicon oxide film on its surface, and a collector region is formed by etching the n-GaAs layer using the collector electrode as a mask. Subsequently to the above process, a base electrode is formed according to a predetermined pattern on the exposed p-GaAs layer. Next, the p-GaAs layer outside the base electrode and the surface part of the underlying n-Al.sub.0.25 Ga.sub.0.75 As layer are removed, and an emitter electrode is formed on the exposed n-Al.sub.0.25 Ga.sub.0.75 As layer.
The thickness of the p-GaAs layer on which is formed the base electrode is determined by an etching process (the base surface revealing process) that forms the collector layer. In the base surface revealing process, a part of the surface of the p-GaAs layer is exposed by etching the overlying n-GaAs layer, but the contact resistance between the base layer and the base electrode becomes high if the etching of the n-GaAs layer is insufficient. Such an increase in the contact resistance can be avoided by etching the surface part of the p-GaAs layer. Since, however, the thickness of the p-GaAs layer underlying the base electrode (the base lead-out region) becomes smaller than that of the active base layer (the part in contact with the collector layer) as a result of such an operation, the base resistance will have to be increased. In practice, the thickness of the base lead-out region has to be made slightly smaller than that of the active base layer in order to avoid the increase in the contact resistance.
Consequently, the adequacy of the above-mentioned process strongly influences the high speed and the high frequency characteristics of the resulting transistor. In addition, the thickness of the base layer has a very small value of 70 to 100 nm so that the nonuniformity in the etching amount within the wafer becomes one of the causes of drastically reducing the uniformity of the characteristics of the elements. Heretofore, it has been very difficult to carry out the above-mentioned process for the entirely of the wafer under a sufficiently satisfactory controllability, and it has been inevitable to have a nonuniformity on the order of 20 nm for 2-inch wafers.
In the case of the emitter-up type HBTs, the base surface revealing process means to etch the AlGaAs layer. In this connection there is a report that it is possible to selectively remove the AlGaAs layer by a wet etching. Namely, according to P. M. Asbeck et al., "GaAlAs/GaAs Heterojunction Bipolar Transistors: Issues and Prospects for Application," IEEE Transactions on Electron Devices, Vol. 36, No. 10, p. 2032, October 1989, it is possible to carry out the surface revealing with a standard deviation of 3 to 4 nm for 2-inch wafers. However, the inventors were unable to confirm this with sufficient reliable reproducibility. In other words, the selective removal of the AlGaAs layer cannot be said to be a sufficiently matured technology. Moreover, from the sense of simplifying the fabrication process, the simultaneous use of a wet etching is not desirable. So far as the dry etching methods are concerned, there is not known a means for selectively removing the AlGaAs layer with respect to the GaAs layer, so that there exist the same problems as for the collector-up type HBTs.